A fundamental design challenge in creating a memory cell of an electrically erasable programmable read only memory (EEPROM) device is to use a controllable and reproducible electrical effect that has sufficient non-linearity so that the memory cell (1) can be written to (or erased) at one voltage in less than one millisecond (1 ms) and can be read at another voltage, and (2) the data within the memory cell must remain unchanged for more than ten (10) years.
Prior art stacked/split gate EEPROM technology requires (1) special multi-polysilicon materials, (2) different gate oxide thicknesses, and (3) modified doping profiles. These prior art requirements create process complexity and high cost when embedded into a complementary metal oxide semiconductor (CMOS) process.
FIG. 1 illustrates a schematic diagram of a prior art memory cell 100 of an electrically erasable programmable read only memory (EEPROM) device. Memory cell 100 comprises one P-channel metal oxide semiconductor (PMOS) transistor 110 and one P-channel metal oxide semiconductor (PMOS) capacitor 120. The PMOS capacitor 120 is formed by connecting together the source, drain and substrate of a PMOS transistor.
The PMOS transistor 110 may be referred to as PMOS program transistor 110. The PMOS capacitor 120 may be referred to as PMOS control capacitor 120. The gate of the PMOS program transistor 110 and the gate of the PMOS control capacitor 120 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 110 and the PMOS control capacitor 120 are collectively referred to as a “floating gate” 130. Charges (in amounts that represent either a zero (“0”) representation or a one (“1”) representation) may be written to the floating gate 130. In order to avoid well bias interference, the PMOS program transistor 110 and the PMOS control capacitor 120 are each located in a separate N well.
The prior art memory cell 100 is written to by injecting drain avalanche hot electrons into the floating gate 130. For PMOS operation (as shown in FIG. 1) low voltage is applied to the control gate and drain of PMOS control capacitor 120 and high voltage is applied to the source/well of PMOS program transistor 110. The channel of PMOS program transistor 110 is turned on and hot electrons are generated at the high electric field region at the drain junction (designated “VINJ” in FIG. 1). With positive voltage on the control gate of PMOS control transistor 120, some hot electrons with high energy will pass through the silicon-silicon dioxide (Si—SiO2) potential barrier and be injected into the floating gate 130.
The prior art memory cell 100 is erased by applying a high voltage to the control gate of the PMOS control transistor 120 and to the ground drain and source of the PMOS program transistor 110. Electrons on the floating gate 130 will pass through the gate oxide between the floating gate 130 and the control gate of the PMOS control capacitor 120 by Fowler-Nordheim (FN) tunneling process and go to the substrate. A description of the physics of the Fowler-Nordheim (FN) tunneling process is set forth in U.S. Pat. No. 5,225,362.
During programming, most control gate voltage should be coupled between the floating gate 130 and the drain/source of the PMOS program transistor 110 to facilitate electron injection to the floating gate 130 but not further to the control gate of the PMOS control transistor 120. This requires the capacitance between the floating gate 130 and the control gate to be large. On the other hand, during the erase procedure, more control gate voltage should be coupled between the floating gate 130 and the control gate, so that electrons can tunnel from the floating gate 130 to the substrate by the Fowler-Nordheim (FN) tunneling process. This requires the capacitance between the floating gate 130 and the control gate to be small.
These two contradictory requirements for the control gate capacitance during the program procedure and the erase procedure leave a narrower operation window. This results in poor data retention and slower speeds for an EEPROM that comprises one PMOS program transistor and one PMOS control capacitor.
To improve the operational speed and data retention for an EEPROM device, EEPROM designers have sometimes placed an additional capacitor in the basic memory cell. This approach has one large capacitor for the programming operation and one small capacitor for the erase operation. Capacitor coupling techniques are used to achieve a favorable electric field for both the programming operation and the erase operation.
The floating gate of an added capacitor has to be filled with hot electrons. Hot electrons that pass through gate oxide will create oxide damage. Oxide damage degrades the endurance of a memory cell. Endurance is measured by how many program/erase cycles the gate oxide can tolerate before unacceptable damage occurs. Therefore, one major drawback to adding an extra capacitor is that it degrades EEPROM memory cell endurance performance.
Another drawback to adding an extra capacitor is that it significantly increases the size of the basic memory cell. This significantly lowers the EEPROM array density. Additional chip area is required for the extra capacitors. This increases the cost.
Another drawback of prior art CMOS EEPROM technology is the speed of the programming procedure. The programming procedure is carried out by utilizing drain avalanche hot electrons. Because the efficiency of generating and injecting the drain avalanche hot electrons is low, programming times are relatively long. The programming time is usually one hundred milliseconds (100 ms) or longer. Even the improved coupling provided by using additional capacitors only reduces the programming time to about twenty milliseconds (20 ms).
FIG. 2 illustrates a schematic diagram of a prior art memory cell 200 of an erasable programmable read only memory (EEPROM) device that comprises a control capacitor and an erase capacitor. Memory cell 200 comprises program transistor 210, control capacitor 220, floating gate 230, erase capacitor 240 and read transistor 250 coupled together as shown in FIG. 2.
Prior art memory cell 200 operates in the same manner as that described for prior art memory cell 100. That is, the gate of the PMOS program transistor 210 and the gate of the PMOS control capacitor 220 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 210 and the PMOS control capacitor 220 are collectively referred to as a “floating gate” 230. Charges (in amounts that represent either a “zero” (“0”) representation or a “one” (“1”) representation) may be written to the floating gate 230.
Prior art memory cell 200 comprises a PMOS erase capacitor 240 to facilitate the erase operation. The gate of the PMOS erase capacitor 240 is also connected to the floating gate 230. Prior art memory cell 200 also comprises a PMOS read transistor 250 to facilitate the read operation. The gate of the PMOS read transistor 250 is also connected to the floating gate 230. The PMOS read transistor 250 has nothing to do with the program/erase operations of memory cell 200.
The programming operation is carried out by Drain Avalanche Hot Carrier (DAHC) electron injection. Electrons from the edge of the drain junction of the program transistor 210 are injected into the floating gate 230. The erase operation is carried out by Fowler-Nordheim (FN) tunneling. Electrons from the floating gate 230 tunnel to the substrate of the erase capacitor 240.
FIG. 3 illustrates an illustrative memory cell layout design 300 for memory cell 200. The program transistor 210 and the erase capacitor 240 and the read transistor 250 are the same size. The program transistor 210 has an area ratio of one to twenty seven (1:27) with respect to the area of the control capacitor 220. During the operation of memory cell 200 this relatively high value for the coupling ratio helps lower the value of the erase voltage and the value of the program voltage.
However, the relatively high value for the coupling ratio leads to excess oxide damage. This is because (1) the large control capacitor 220 has to be filled up from a small hot electron injection point, and (2) during the erase process all the electrons stored on the large control capacitor 220 must be removed from a small erase point. This is one of the major reasons that complementary metal oxide semiconductor (CMOS) non-volatile memory (NVM) memory cells usually are capable of only one thousand (1,000) or so program/erase cycles.
Complementary metal oxide semiconductor (CMOS) non-volatile memory (NVM) memory cells should be able to perform one thousand (1,000) program/erase cycles and have a program time of approximately twenty milliseconds (20 ms). However, some CMOS NVM memory cells were found to not meet the required levels of performance. In particular, after about two hundred fifty (250) program/erase cycles some CMOS NVM memory cells became “weak programmed.” The term “weak programmed” means that the read current of a memory cell becomes lower than the desired level for the read current. As the number of program/erase cycles increased, the number of failures (i.e., the number of “weak programmed” memory cells) also increased.
An investigation revealed that there are three principal factors that contribute to the creation of “weak programmed” memory cells. The first contribution is that the program/erase process causes degradation of the program current. Lower values of program current are directly related to the creation of “weak programmed” memory cells.
Experiments were conducted on a 0.44 micron by 0.40 micron metal oxide semiconductor field effect transistor (MOSFET) having a gate oxide thickness of seventy Ångstroms (70 Å). Experimental data showed that if the memory cells are programmed with Drain Avalanche Hot Carrier (DAHC) programming for twenty seconds (20 s), then the program current (IG) decreases by over fifty percent (50%). If one cycle time is one hundred milliseconds (100 ms), then the DAHC stress time of twenty seconds (20 s) is equivalent to two hundred (200) program cycles.
FIG. 4 illustrates this feature in a graph 400 of program current (IG) in amperes (A) versus time in seconds (s). The drain voltage (VD) is negative six volts (−6 V) and the gate voltage (VG) is negative one and one tenth volt (−1.1 V). As shown in FIG. 4, under a constant DAHC stress, the value of the program current (i.e., the DAHC gate injection current) (IG) decreases from approximately 2.75×10−10 amperes to approximately 1.04×10−10 amperes in twenty seconds (20 s). Lower program current inevitably causes “weak programmed” memory cells.
The second factor that contributes to the creation of “weak programmed” memory cells comes from the fact that the EEPROM memory cell ramps up the control gate voltage during the programming process. The ramp up of control gate voltage compensates for the floating gate voltage drop that is due to the injection of more hot electrons. However, as more and more program/erase cycles occur, the program current (i.e., the DAHC gate injection current) (IG) decreases, but the control gate voltage ramps up as normal. This phenomenon increases the floating gate voltage (VFG), which decreases the channel current in the program transistor 210. Decreasing the channel current during the programming process inevitably leads to the creation of “weak programmed” memory cells.
The third factor that contributes to the creation of “weak programmed” memory cells comes from the fact that the Drain Avalanche Hot Carrier (DAHC) programming process is sensitive to the CMOS process. A change of fifty millivolts (50 mV) in the threshold voltage (Vth) is well within CMOS specifications. However, such a change can lead to a ten percent (10%) variation in the value of program current (IG). The value of the program current (IG) is also affected by other parameters, such as drain/source series resistance, drain junction doping, gate oxide thickness variation, etc. Large variations in program current (IG) may lead to increased stress in memory cells and cause early failure in the affected memory cells.
Although CMOS non-volatile memory (NVM) memory cells are relatively low in cost, they are capable of only about one thousand (1,000) program/erase cycles. This is a low level of endurance that is significantly less than the one hundred thousand (100,000) program/erase cycles that a floating gate tunneling oxide transistor (FLOTOX) EEPROM device can provide. An example of a prior art FLOTOX EEPROM device is described in U.S. Pat. No. 5,225,362.
Although FLOTOX EEPROM devices have a high level of endurance, they are more complicated and more expensive. For example, the prior art FLOTOX EEPROM device shown in U.S. Pat. No. 5,225,362 has a double polysilicon technology and special tunnel windows. The cost of embedding such an EEPROM device into a CMOS platform is rather high because many manufacturing process steps have to be changed or added to the basic CMOS process. That is, the manufacturing process for the FLOTOX EEPROM devices is basically not CMOS compatible. On the other hand, the cost of embedding CMOS compatible EEPROM devices into a CMOS platform is very low.
Therefore, there is a need in the art for a system and method that is capable of solving the poor performance problems described above that are exhibited by prior art memory cells in electrically erasable programmable read only memory (EEPROM) devices. In particular, there is a need in the art for a system and method for providing EEPROM devices that combine the high endurance features of the more expensive EEPROM devices and the low manufacturing costs of the CMOS compatible EEPROM devices. There is a need in the art for a system and method for providing high endurance, low cost CMOS compatible EEPROM devices.
The present invention provides a high endurance, low cost CMOS compatible EEPROM memory cell that comprises three CMOS N type (NMOS) transistors. The first NMOS transistor serves as a control capacitor, the second NMOS transistor serves as an erase capacitor, and the third NMOS transistor serves as a program capacitor. The gates of the three NMOS transistors are connected together to form a floating gate.
The control capacitor is implemented by connecting together the source and the drain and the P well of the transistor. The erase capacitor is also implemented by connecting together the source and the drain and the P well of the transistor. The source and the P well of the transistor of the program capacitor are connected together but the drain of the program capacitor is separate so that the transistor of the program capacitor can also serve as a read transistor during read operations. The source and the drain and the P well of the program transistor are all three connected to a program voltage during the programming operation.
Each NMOS transistor of the EEPROM memory cell is isolated from the underlying P substrate by a Deep N Well isolation structure. This allows the well bias voltage to be isolated from other active elements on the semiconductor wafer.
In CMOS non-volatile memory (NVM) devices, the Drain Avalanche Hot Carrier (DAHC) programming operation creates more oxide damage than does the Fowler-Nordheim (FN) programming operation. The EEPROM memory cell of the present invention provides a high level of endurance (as measured by the number of program/erase cycles that can be performed) because it employs the Fowler-Nordheim (FN) tunneling method for both the programming operation and the erase operation. In addition, because the programming operation and the erase operation are conducted through two transistor gate oxides (instead of one transistor gate oxide), the damage to the gate oxide of the transistors is shared between two transistors. Therefore the EEPROM memory cell of the present invention can tolerate an increased number of program/erase cycles.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.